Paraphernalia
PPubMed30 Jun 2026

An efficient multiplier-based FPGA CNN accelerator for Parkinson's disease detection using hand-drawn circle images

VedanthSrivatson A., Sivanantham Sathasivam, Prakash Ramachandran

Abstract

Introduction This study presents a Field-Programmable Gate Array (FPGA)-based convolutional neural network (CNN) accelerator for preliminary Parkinson's disease (PD) handwriting classification using hand-drawn circle images, with emphasis on arithmetic-level optimization through efficient multiplier architectures. Although optimized multipliers have been extensively studied for machine learning acceleration, their application-specific effects on inference consistency and hardware efficiency in healthcare-oriented FPGA implementations remain underexplored. Methods To address this issue, a lightweight binary CNN classifier, trained on Google Colab, is deployed on FPGA hardware and evaluated with three multiplier architectures: standard multipliers, approximate logarithmic multipliers, and Karatsuba multipliers. The desktop CNN model was evaluated using both non-augmentation validation and standard augmentation strategies. The primary evaluation methodology used a non-augmentation validation approach, in which augmentation was applied exclusively to the training set, resulting in a software validation accuracy of 92.86%. The standard augmentation strategy achieved a validation accuracy of 97.83% and was used to compare the effects of augmentation before splitting. The trained model was quantized to Q4.12 fixed-point precision and implemented on FPGA hardware, where dense-layer computations were performed using different multiplier architectures. Hardware inference was validated on the NewHandPD hand-drawn circle dataset, and FPGA outputs were compared with software inference results via graphical analysis and Mean Absolute Deviation (MAD) to assess numerical consistency. Results Experimental results indicate that the FPGA-based implementation achieved classification behavior closely aligned with software inference while improving hardware efficiency. Under the non-augmentation validation approach, the FPGA implementation achieved 89.73% accuracy compared to 92.86% in software, whereas the standard augmentation strategy achieved 95.40% accuracy compared to 97.83% in software using the Approximate Logarithmic Multiplier.

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