27 papers · ranked by Valyu relevance
Alexander Fusco, Sahil Hassan, Joshua Mack, Ali Akoglu
—Non-uniform performance and power consumption across the processing elements (PEs) of heterogeneous SoCs increase the computation complexity of the task scheduling problem compared to homogeneous architectures. Latency of a software-based scheduler with the increased heterogeneity level in terms of number and types of…
Vivek Parmar, Bogdan Penkovsky, Damien Querlioz, Manan Suri
With recent advances in the field of artificial intelligence (AI) such as binarized neural networks (BNNs), a wide variety of vision applications with energy-optimized implementations have become possible at the edge. Such networks have the first layer implemented with high precision, which poses a challenge in…
Alexej Schatz, York Winter
Single-board computers such as the Raspberry Pi make it easy to control hardware setups for laboratory experiments. GPIOs and expansion boards (HATs) give access to a whole range of sensor and control hardware. However, controlling such hardware can be challenging, when many experimental setups run in parallel and the…
Lei Deng, Huajin Tang, Kaushik Roy
Neuromorphic models enjoy low computational costs owing to the binary spike representation and sparse operations. However, directly executing SNNs on GPUs without tailored optimization is inefficient. Neuromorphic hardware is designed for the efficient execution of SNNs via event-driven computing (Merolla et al., ). In…
Pervesh Kumar, Huo Yingge, Imran Ali, Young-Gun Pu + 7 more
'Keum-Cheol Hwang' 'Youngoo Yang' 'Yeon-Jae Jung' 'Hyung-Ki Huh' 'Seok-Kee Kim' 'Joon-Mo Yoo' 'Kang-Yoon Lee'] This paper presents a register-transistor level (RTL) based convolutional neural network (CNN) for biosensor applications. Biosensor-based diseases detection by DNA identification using biosensors is currently…
Zofia Długosz, Michał Rajewski, Rafał Długosz, Tomasz Talaśka + 1 more
'Adam Krzyzak'] In this work, we propose a novel metaheuristic algorithm that evolved from a conventional particle swarm optimization (PSO) algorithm for application in miniaturized devices and systems that require low energy consumption. The modifications allowed us to substantially reduce the computational complexity…
Kazutomo Yoshii, Rajesh Sankaran, Sebastian Strempfer, Maksim Levental + 2 more
'Maksim Levental' 'M. Hammer' 'Antonino Miceli'] As spatial and temporal resolutions of scientific instruments improve, the explosion in the volume of data produced is becoming a key challenge. It can be a critical bottleneck for integration between scientific instruments at the edge and high-performance…
Leila Bagheriye, Johan Kwisthout
The implementation of inference (i.e., computing posterior probabilities) in Bayesian networks using a conventional computing paradigm turns out to be inefficient in terms of energy, time, and space, due to the substantial resources required by floating-point operations. A departure from conventional computing systems…
Yuehai Chen, Huarun Chen, Shaozhen Chen, Chao Han + 6 more
'Yijun Liu' 'Huihui Zhou' 'Mikolaj Karpinski' 'Oleksandr O. Kuznetsov' 'Oleksandr V. Lemeshko'] A Trusted Execution Environment (TEE) is an efficient way to secure information. To obtain higher efficiency, the building of a dual-core system-on-chip (SoC) with TEE security capabilities is the hottest topic. However, TEE…
Yusuke Shinji, Hirotsugu Okuno, Yutaka Hirata
The cerebellum plays a central role in motor control and learning. Its neuronal network architecture, firing characteristics of component neurons, and learning rules at their synapses have been well understood in terms of anatomy and physiology. A realistic artificial cerebellum with mimetic network architecture and…
Jesús Fernández-Conde, Gwanggil Jeon
In real-time data-intensive applications, achieving real-time data acquisition from sensors and simultaneous storage with the necessary performance is challenging, especially if “no-data-lost” requirements are present. Ad hoc solutions are generally expensive and suffer from a lack of modularity and scalability. In…
Kiran Magar, Shreya Bharathan, Utsav Banerjee
—Probabilistic computing is an emerging quantuminspired computing paradigm capable of solving combinatorial optimization and various other classes of computationally hard problems. In this work, we present pc-COP, an efficient and configurable probabilistic computing hardware accelerator with 2048 fully connected…
Wiktoria Agata Pawlak, Newton Howard
Neuromorphic computing technologies are about to change modern computing, yet most work thus far has emphasized hardware development. This review focuses on the latest progress in algorithmic advances specifically for potential use in brain implants. We discuss current algorithms and emerging neurocomputational models…
Chakrabarti, Aradhya
—Soft-core processors on resource-constrained FPGAs often suffer from low code density and reliance on proprietary toolchains. This paper details the design, implementation, and evaluation of a 32-bit dual-stack microprocessor architecture optimized for low-cost, resource-constrained Field-Programmable Gate Arrays…
Jérémie Laydevant, Logan G. Wright, Tianyu Wang, Peter L. McMahon
Human brains and bodies are not hardware running software: the hardware is the software. We reason that because the microscopic physics of artificial-intelligence hardware and of human biological "hardware" is distinct, neuromorphic engineers need to be cautious (and yet also creative) in how we take inspiration from…
M.F. Chowdhury, Mostafizur Rahman
Architecture Authors: ['M.F. Chowdhury' 'Mostafizur Rahman'] Abstract— Addressing the growing demands of artificial intelligence (AI) and data analytics requires new computing approaches. In this paper, we propose a reconfigurable hardware accelerator designed specifically for AI and dataintensive applications. Our…
M. Di Florio, Y. Bornat, M. Caré, V. R. Cota + 2 more
This study addresses the inherent difficulties in the creation of neuroengineering devices for closed-loop stimulation, a task typically characterized by intricate and technically demanding processes. Beneath the substantial hardware advancements in neurotechnology, there is often rather complex low-level code that…
Junwen Luo
Neural ptosthetic devices offer the ability to develop novel treatments for previously incurable diseases and ailments, such as deafness, blindness and tetraplepia. There is the potential to extend this concept to incorporate cognitive prosthetics, whereby damaged individual neuron cells or larger brain regiops are…
George Dimitriadis, Ella Svahn, Andrew MacAskill, Athena Akrami
To realise a research project idea, an experimenter faces a series of conflicting design and implementation considerations, regarding both its hardware and software components. For instance, the ease of implementation, in time and expertise, should be balanced against the ease of future reconfigurability and number of…
Michael Kissner, Leonardo Del Bino, Felix Päsler, Peter Caruana + 1 more
'George N. Ghalanos'] Abstract—Energy efficiency of electronic digital processors is primarily limited by the energy consumption of electronic communication and interconnects. The industry is almost unanimously pushing towards replacing both long-haul, as well as local chip interconnects, using optics to drastically…
Authors not listed
Nondestructive ultrasonic testing is finding increasing use in battery science. We provide instructions and software for the development of a low cost, modular, and easy to use scanning acoustic microscope. Basic principles of ultrasonic testing are discussed with particular attention to its application for operando…
Erin Looney, Andre Buscariolli, Maria Yang, Geoffrey Raymond + 2 more
Hardware-based startups risk having longer times-to-market, deterring investment in critical fields such as cleantech, medical devices, and automation. We interviewed 55 leaders at hardware startups, mapped their development timelines, and found prototyping to be the longest development step (median of 19 weeks per…
Madushanka Manathunga, Hasan Metin Aktulga, Andreas W. Goetz, Kenneth M. Merz + 1 more
We have ported and optimized the GPU accelerated QUICK and AMBER based ab initio QM/MM implementation on AMD GPUs. This encompasses the entire Fock matrix build and force calculation in QUICK including one-electron integrals, two-electron repulsion integrals, exchange-correlation quadrature, and linear algebra…
Authors not listed
An automatic code generated C++/HIP/CUDA implementation of the (auxiliary) Fock, or Kohn–Sham, matrix construction for execution in GPU-accelerated hardware environments is presented. The module is developed as part the quantum chemistry software package VeloxChem, employing localized Gaussian atomic orbitals. The per-…
Peter Kraus, Edan Bainglass, Francisco F. Ramirez, Enea Svaluto-Ferro + 7 more
Compliance with good research data management practices means trust in the integrity of the data, and it is achievable by a full control of the data gathering process. In this work, we demonstrate tooling which bridges these two aspects, and illustrate its use in a case study of automated battery cycling. We…
Pierre Tremouilhac, Matthias Döring, Johannes Haubold, sylvia Vanderheiden + 4 more
The digitalization of processes in experimental laboratories often encounters obstacles with devices that lack connectivity with other systems. We propose a method to record and use values from such devices, demonstrating its effectiveness for weighing processes conducted using laboratory balances. Our developments…
Natalia Cherezova, Dmitri Mihhailov, Sergei Devadze, Artur Jutman
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